The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
The ever-shrinking geometry size brings challenges to semiconductor fabrication. To achieve smaller dimensions, a shrink material may be applied on photoresist patterns to reduce the dimensions between adjacent photoresist patterns. However, the reductions of these dimensions may be affected by different profiles of the developed photoresist patterns, or by the number of deprotected acid labile group (ALG) units of the photoresist patterns. As a result, the use of shrink material may not bring about the desired reduction in device dimensions.
Therefore, while existing photolithography processes have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.